Description
Not Recommended for New Design CY7C1386D CY7C1387D 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM 18-Mbit (512K × 36/1M × 18) Pipelined DCD Syn.
The CY7C1386D/CY7C1387D SRAM integrates 512K × 36/1M × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal.
Features
* Supports bus operation up to 200 MHz
* Available speed grades are 200, and 167 MHz
* Registered inputs and outputs for pipelined operation
* Optimal for performance (double-cycle deselect)
* Depth expansion without wait state
* 3.3 V core power supply (VDD)
* 2.5 V or 3
