Description
1CY7C1380BV25 PRELIMINARY CY7C1380BV25 CY7C1382BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM .
The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal techn.
Features
* Fast clock speed: 200,166, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns Optimal for depth expansion 2.5V (±5%) Operation Common d
Applications
* High-density, high-speed packages
* JTAG boundary scan for BGA packaging version (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), burst control in, and ADV), Write Enables (BWa, BWb, puts (ADSC, ADSP BWc, BWd and BWE), and g
