CY7C1386S Datasheet (Cypress) - 18-Mbit (512 K x 36) Pipelined DCD Sync SRAM

CY7C1386S, 18-Mbit (512 K x 36) Pipelined DCD Sync SRAM

The CY7C1386S SRAM integrates 512 K × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

The synchronous inputs include all addresses

CY7C1386S Features

* Supports bus operation up to 167 MHz

* Available speed grade is 167 MHz

* Registered inputs and outputs for pipelined operation

* Optimal for performance (double-cycle deselect)

* Depth expansion without wait state

* 3.3 V core power supply (VDD)

* 2.5 V or 3.3 V I/O po