CY7C1386S Datasheet - Cypress

CY7C1386S 18-Mbit (512 K x 36) Pipelined DCD Sync SRAM

The CY7C1386S SRAM integrates 512 K × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses.

CY7C1386S Features

* Supports bus operation up to 167 MHz

* Available speed grade is 167 MHz

* Registered inputs and outputs for pipelined operation

* Optimal for performance (double-cycle deselect)

* Depth expansion without wait state

* 3.3 V core power supply (VDD)

* 2.5 V or 3.3 V I/O po

CY7C1386S-Cypress.pdf

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Datasheet Details

Part number:

CY7C1386S

Manufacturer:

Cypress

File Size:

520.16 KB

Description:

18-mbit (512 k x 36) pipelined dcd sync sram.

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TAGS

CY7C1386S CY7C1386S 18-Mbit 512 Pipelined DCD Sync SRAM Cypress

CY7C1386S Distributor