CY7C1386C Datasheet (Cypress Semiconductor) - (CY7C1386C / CY7C1387C) 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM

CY7C1386C, (CY7C1386C / CY7C1387C) 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM

1] The CY7C1386C/CY7C1387C SRAM integrates 524,288 x 36 and 1048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

The synchro

CY7C1386C Features

* Supports bus operation up to 250 MHz

* Available speed grades are 250, 225, 200 and 167 MHz

* Registered inputs and outputs for pipelined operation

* Optimal for performance (Double-Cycle deselect)

* Depth expansion without wait state

* 3.3V