CY7C1425AV18 - 36-Mbit QDR-II SRAM 2-Word Burst Architecture
The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.
QDR-II architecture consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read operations and the Write Po
CY7C1425AV18 Features
* Separate Independent Read and Write data ports
* Supports concurrent transactions
* 250-MHz clock for high bandwidth
* 2-Word Burst on all accesses
* Double Data Rate (DDR) interfaces on both Read and Write www.DataSheet4U.com ports (data transferred at 500
