CY7C1425KV18 - 36-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1425KV18 Features
* Separate independent read and write data ports
* Supports concurrent transactions
* 333 MHz clock for high bandwidth
* Two-word burst on all accesses
* Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
* Two input clocks
