CY7C1425KV18 Datasheet - Cypress Semiconductor

36-Mbit QDR II SRAM Two-Word Burst Architecture

* Separate independent read and write data ports

* Supports concurrent transactions

* 333 MHz clock for high bandwidth

* Two-word burst on all accesses

* Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz

* Two input clocks

CY7C1425KV18

Cypress Semiconductor

1.26 MB

36-mbit qdr ii sram two-word burst architecture.

📁 Related Datasheet

CY7C1425AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture (Cypress Semiconductor)

CY7C1425JV18 (CY7C14xxJV18) SRAM 2-Word Burst Architecture (Cypress Semiconductor)

CY7C1425V18 (CY7C14xxV18) SRAM 2-Word Burst Architecture (Cypress Semiconductor)

CY7C142 2K x 8 Dual-Port Static RAM (Cypress Semiconductor)

CY7C1420AV18 (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture (Cypress Semiconductor)

CY7C1420BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture (Cypress Semiconductor)

CY7C1420JV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture (Cypress Semiconductor)

CY7C1420KV18 36-Mbit DDR II SRAM Two-Word Burst Architecture (Cypress Semiconductor)

CY7C1421AV18 1.8V Synchronous Pipelined SRAM (Cypress Semiconductor)

CY7C1422AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture (Cypress Semiconductor)

TAGS

Image Gallery