CY7C1444AV33 Datasheet - Cypress Semiconductor

CY7C1444AV33 - 36-Mbit Pipelined DCD Sync SRAM

The CY7C1444AV33 SRAM integrates 1M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for

CY7C1444AV33 Features

* Supports bus operation up to 250 MHz

* Available speed grades are 250 MHz and 167 MHz

* Registered inputs and outputs for pipelined operation

* Optimal for performance (double-cycle deselect)

* Depth expansion without wait state

* 3.3 V core power supply

* 2.5 V/3.3 V I

Datasheet Details

CY7C1444AV33

Cypress Semiconductor

482.65 KB

36-mbit pipelined dcd sync sram.

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