SSTE32882HLB - 1.35V/1.5V REGISTERING CLOCK DRIVER

Name: SSTE32882HLB
SKU: SSTE32882HLB-1416247

Renesas

Datasheet Details

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operation.

Pinout optimizes DDR3 RDIMM PCB layout.
1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs.
Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs.
Supports LVCMOS switching levels on the RESET and MIRROR inputs.
Checks priority on DIMM-independent data inputs.
Supports dynamic 1T/3T timing transaction and output inversion feature for imp.

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Published: Jan 19, 2020 |