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MS90C104 Datasheet Preview

MS90C104 Datasheet

30bits COLOR LVDS Receiver

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MS90C104
MS90C104
——+3.3V 175MHz 30bits COLOR LVDS Receiver
General Description
The MS90C104 receiver is designed to support pixel data transmission
between Host and Flat Panel Display from NTSC up to SXGA resolutions. The
MS90C104 converts the LVDS data streams back into 35bits of CMOS/TTL
data with the choice of the rising edge or falling edge clock for the convenience
with a variety of LCD panel controllers. At a transmit clock frequency of
175Mhz, 30bits of GRB data and 5bits of timing and control data
(HSYNC,VSYCN,DE,CNTL1,CNTL2) are transmitted at an effective rate of
1225Mbps per LVDS channel. Using a 175MHz clock, the data throughput is
765.6Mbytes/sec.
Features
Clock range:8-175MHz
Narrow bus reduces cable size
Single 3.3V supply
Power-down Mode
Supports VGA、SVGA、XGA、SXGA
Up to 6.125Gbps throughput
Up to 765.6Megabytes/sec bandwidth
PLL requires no external components
Compatible with TIA/EIA-644 LVDS standard
TQFP64 Package
Hangzhou Ruimeng Technology Co.,LTD
Http: www.relmon.com
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Ruimeng

MS90C104 Datasheet Preview

MS90C104 Datasheet

30bits COLOR LVDS Receiver

No Preview Available !

Pin Diagram
MS90C104
Pin Description
Pin Name
RL0+,RL0-
RL1+, RL1-
RL2+, RL2-
RL3+, RL3-
RL4+, RL4-
RCLK+, RCLK-
Pin No.
49, 50
51, 52
54, 55
59, 60
61,62
56, 57
RxOUT0 ~ RxOUT6
RxOUT7 ~ RxOUT13
RxOUT14 ~ RxOUT20
RxOUT21 ~ RxOUT27
47,46,45,43,42,20,41
40,39,38,19,18,36,35
34,33,17,15,32,29,28
27,26,14,25,24,22,21
I/O
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
OUT
OUT
OUT
OUT
Description
LVDS differential data
inputs
LVDS differential clock
inputs
TTL level data outputs.
This includes:10 RED,10
GREEN,10 BLUE,5 control
lines (HSYNC,VSYNC,DE,
Hangzhou Ruimeng Technology Co.,LTD
Http: www.relmon.com
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Part Number MS90C104
Description 30bits COLOR LVDS Receiver
Maker Ruimeng
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