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SST29EE512 Datasheet Preview

SST29EE512 Datasheet

512 Kilobit (64K x8) Page-Mode EEPROM

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SST29EE512 pdf
512 Kilobit (64K x8) Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
FEATURES:
• Single Voltage Read and Write Operations
– 5.0V-only for SST29EE512
– 3.0-3.6V for SST29LE512
– 2.7-3.6V for SST29VE512
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
• Fast Page-Write Operation
– 128 Bytes per Page, 512 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 2.5 sec (typical)
– Effective Byte-Write Cycle
Time: 39 µs (typical)
Data Sheet
• Fast Read Access Time
– 5.0V-only operation: 70 and 90 ns
– 3.0-3.6V operation: 150 and 200 ns
– 2.7-3.6V operation: 200 and 250 ns
• Latched Address and Data
• Automatic Write Timing
– Internal VPP Generation
• End of Write Detection
– Toggle Bit
– Data# Polling
• Hardware and Software Data Protection
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32 Pin PDIP
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 14mm, 8mm x 20mm)
PRODUCT DESCRIPTION
The SST29EE512/29LE512/29VE512 are 64K x8
CMOS, Page-Write EEPROMs manufactured with
SST’s proprietary, high performance CMOS
SuperFlash technology. The split-gate cell design and
thick oxide tunneling injector attain better reliability
and manufacturability compared with alternate ap-
proaches. The SST29EE512/29LE512/29VE512 write
with a single power supply. Internal Erase/Program is
transparent to the user. The SST29EE512/29LE512/
29VE512 conform to JEDEC standard pinouts for byte-
wide memories.
Featuring high performance Page-Write, the
SST29EE512/29LE512/29VE512 provide a typical
Byte-Write time of 39 µsec. The entire memory, i.e., 64
KBytes, can be written page-by-page in as little as 2.5
seconds, when using interface features such as
Toggle Bit or Data# Polling to indicate the completion
of a Write cycle. To protect against inadvertent write,
the SST29EE512/29LE512/29VE512 have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spec-
trum of applications, the SST29EE512/29LE512/
29VE512 are offered with a guaranteed Page-Write
endurance of 104 cycles. Data retention is rated at
greater than 100 years.
The SST29EE512/29LE512/29VE512 are suited for ap-
plications that require convenient and economical updat-
ing of program, configuration, or data memory. For all
system applications, the SST29EE512/29LE512/
29VE512 significantly improve performance and reliabil-
ity, while lowering power consumption. The
SST29EE512/29LE512/29VE512 improve flexibility
while lowering the cost for program, data, and configura-
tion storage applications.
To meet high density, surface mount requirements, the
SST29EE512/29LE512/29VE512 are offered in 32-pin
TSOP (8mm x 14mm and 8mm x 20mm) and 32-lead
PLCC packages. A 600-mil, 32-pin PDIP package is also
available. See Figures 1 and 2 for pinouts.
Device Operation
The SST Page-Mode EEPROM offers in-circuit electri-
cal write capability. The SST29EE512/29LE512/
29VE512 do not require separate Erase and Program
operations. The internally timed Write cycle executes
both erase and program transparently to the user. The
SST29EE512/29LE512/29VE512 have industry stan-
dard optional Software Data Protection, which SST
recommends always to be enabled. The SST29EE512/
29LE512/29VE512 are compatible with industry stan-
dard EEPROM pinouts and functionality.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
© 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
301-3 6/00
1
SSF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.



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SST29EE512 Datasheet Preview

SST29EE512 Datasheet

512 Kilobit (64K x8) Page-Mode EEPROM

No Preview Available !

SST29EE512 pdf
512 Kilobit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Read
The Read operations of the the SST29EE512/29LE512/
29VE512 are controlled by CE# and OE#, both have to be
low for the system to obtain data from the outputs. CE#
is used for device selection. When CE# is high, the chip
is deselected and only standby power is consumed. OE#
is the output control and is used to gate data from the
output pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the read cycle timing
diagram for further details (Figure 3).
Write
The Page-Write to the SST29EE512/29LE512/29VE512
should always use the JEDEC Standard Software Data
Protection (SDP) three-byte command sequence. The
SST29EE512/29LE512/29VE512 contain the optional
JEDEC approved Software Data Protection scheme.
SST recommends that SDP always be enabled, thus, the
description of the Write operations will be given using the
SDP enabled format. The three-byte SDP Enable and
SDP Write commands are identical; therefore, any
time a SDP Write command is issued, Software Data
Protection is automatically assured. The first time the
three-byte SDP command is given, the device becomes
SDP enabled. Subsequent issuance of the same com-
mand bypasses the data protection for the page being
written. At the end of the desired Page-Write, the entire
device remains protected. For additional descriptions,
please see the application notes on “The Proper Use of
JEDEC Standard Software Data Protection” and “Pro-
tecting Against Unintentional Writes When Using Single
Power Supply Flash Memories” in this data book.
The Write operation consists of three steps. Step 1 is the
three-byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
SST29EE512/29LE512/29VE512. Steps 1 and 2 use
the same timing for both operations. Step 3 is an in-
ternally controlled write cycle for writing the data loaded
in the page buffer into the memory array for nonvolatile
storage. During both the SDP three-byte load sequence
and the byte-load cycle, the addresses are latched by the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched by the rising edge of either CE# or
WE#, whichever occurs first. The internal write cycle is
initiated by the TBLCO timer after the rising edge of WE#
or CE#, whichever occurs first. The Write cycle, once
initiated, will continue to completion, typically within 5 ms.
See Figures 4 and 5 for WE# and CE# controlled Page-
Write cycle timing diagrams and Figures 14 and 16 for
flowcharts.
The Write operation has three functional cycles: the
Software Data Protection load sequence, the page load
cycle, and the internal Write cycle. The Software Data
Protection consists of a specific three byte-load se-
quence that allows writing to the selected page and will
leave the SST29EE512/29LE512/29VE512 protected at
the end of the Page-Write. The page load cycle consists
of loading 1 to 128 Bytes of data into the page buffer. The
internal Write cycle consists of the TBLCO time-out and
the write timer operation. During the Write operation, the
only valid reads are Data# Polling and Toggle Bit.
The Page-Write operation allows the loading of up to 128
Bytes of data into the page buffer of the SST29EE512/
29LE512/29VE512 before the initiation of the internal
Write cycle. During the internal Write cycle, all the data in
the page buffer is written simultaneously into the memory
array. Hence, the Page-Write feature of SST29EE512/
29LE512/29VE512 allows the entire memory to be writ-
ten in as little as 2.5 seconds. During the internal Write
cycle, the host is free to perform additional tasks, such as
to fetch data from other locations in the system to set up
the write to the next page. In each Page-Write operation,
all the bytes that are loaded into the page buffer must
have the same page address, i.e. A7 through A16. Any
byte not loaded with user data will be written to FF.
See Figures 4 and 5 for the Page-Write cycle timing
diagrams. If after the completion of the three-byte SDP
load sequence or the initial byte-load cycle, the host
loads a second byte into the page buffer within a byte-
load cycle time (TBLC) of 100 µs, the SST29EE512/
29LE512/29VE512 will stay in the page load cycle.
Additional bytes are then loaded consecutively. The
page load cycle will be terminated if no additional byte is
loaded into the page buffer within 200 µs (TBLCO) from the
last byte-load cycle, i.e., no subsequent WE# or CE#
high-to-low transition after the last rising edge of WE# or
CE#. Data in the page buffer can be changed by a
subsequent byte-load cycle. The page load period can
continue indefinitely, as long as the host continues to
load the device within the byte-load cycle time of 100 µs.
The page to be loaded is determined by the page address
of the last byte loaded.
Software Chip-Erase
The SST29EE512/29LE512/29VE512 provide a Chip-
Erase operation, which allows the user to simultaneously
clear the entire memory array to the “1” state. This is
useful when the entire device must be quickly erased.
© 2000 Silicon Storage Technology, Inc.
2
301-3 6/00


Part Number SST29EE512
Description 512 Kilobit (64K x8) Page-Mode EEPROM
Maker SST
Total Page 26 Pages
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