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PSD813F1-A Datasheet

Flash In-System Programmable (ISP) Peripherals

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PSD813F1-A
Flash In-System Programmable (ISP) Peripherals
For 8-bit MCUs
PRELIMINARY DATA
FEATURES SUMMARY
s Single Supply Voltage:
– 5 V±10% for PSD813F1-A
– 3.3 V±10% for PSD813F1-AV
s Up to 1Mbit of Primary Flash Memory (8 uniform
sectors)
s 256Kbit Secondary EEPROM (4 uniform
sectors)
s Up to 16Kbit SRAM
s Over 3,000 Gates of PLD: DPLD and CPLD
s 27 Reconfigurable I/O ports
s Enhanced JTAG Serial Port
s Programmable power management
s High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 10,000 Erase/Write Cycles of EEPROM
– 1,000 Erase/Write Cycles of PLD
Figure 1. Packages
PQFP52 (T)
PLCC52 (K)
January 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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STMicroelectronics Electronic Components Datasheet

PSD813F1-A Datasheet

Flash In-System Programmable (ISP) Peripherals

No Preview Available !

Revision A Flash PSD
PSD813F1-A
Flash In-System-Programmable Microcontroller Peripherals
Table of Contents
1.0 Introduction ...........................................................................................................................................................1
2.0 Key Features ........................................................................................................................................................2
PSD813F1 Block Diagram .............................................................................................................................4
3.0 General Information ..............................................................................................................................................5
4.0 PSD813F1 Family.................................................................................................................................................5
5.0 PSD813F1 Architectural Overview .......................................................................................................................6
5.1 Memory...................................................................................................................................................6
5.2 Page Register .........................................................................................................................................6
5.3 PLDs .......................................................................................................................................................6
5.4 I/O Ports..................................................................................................................................................7
5.5 Microcontroller Bus Interface ..................................................................................................................7
5.6 JTAG Port ...............................................................................................................................................7
5.7 In-System Programming .........................................................................................................................8
5.8 Power Management................................................................................................................................8
6.0 Development System............................................................................................................................................9
7.0 PSD813F1 Pin Descriptions ...............................................................................................................................10
8.0 PSD813F1 Register Description and Address Offset .........................................................................................14
9.0 PSD813F1 Functional Blocks .............................................................................................................................15
9.1 Memory Blocks .....................................................................................................................................15
9.1.1 Main Flash and Secondary EEPROM ........................................................................................15
9.1.2 SRAM .........................................................................................................................................29
9.1.3 Memory Select Signals...............................................................................................................29
9.1.4 Page Register.............................................................................................................................32
9.2 PLDs .....................................................................................................................................................33
9.2.1 Decode PLD (DPLD) ..................................................................................................................35
9.2.2 Complex PLD (CPLD) ................................................................................................................35
9.3 Microcontroller Bus Interface ................................................................................................................44
9.3.1 PSD813F Interface to a Multiplexed 8-bit Bus ...........................................................................44
9.3.2 PSD813F Interface to a Non-Multiplexed 8-bit Bus....................................................................44
9.3.3 Data Byte Enable Reference......................................................................................................47
9.3.4 Microcontroller Interface Examples ............................................................................................47
9.4 I/O Ports................................................................................................................................................52
9.4.1 General Port Architecture...........................................................................................................52
9.4.2 Port Operating Modes ................................................................................................................54
9.4.3 Port Configuration Registers (PCRs) .........................................................................................57
9.4.4 Port Data Registers ....................................................................................................................60
9.4.5 Ports A and B – Functionality and Structure ............................................................................61
9.4.6 Port C – Functionality and Structure ........................................................................................63
9.4.7 Port D – Functionality and Structure ........................................................................................63
9.5 Power Management..............................................................................................................................67
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode .....................................................67
9.5.2 Other Power Saving Options......................................................................................................71
9.5.3 Reset and Power On Requirement ............................................................................................72
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Part Number PSD813F1-A
Description Flash In-System Programmable (ISP) Peripherals
Maker STMicroelectronics
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