• Part: PSD813F1-A
  • Description: Flash In-System Programmable (ISP) Peripherals
  • Manufacturer: STMicroelectronics
  • Size: 553.43 KB
Download PSD813F1-A Datasheet PDF
STMicroelectronics
PSD813F1-A
PSD813F1-A is Flash In-System Programmable (ISP) Peripherals manufactured by STMicroelectronics.
Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs PRELIMINARY DATA Features SUMMARY s Single Supply Voltage: - 5 V±10% for PSD813F1-A - 3.3 V±10% for PSD813F1-AV s Up to 1Mbit of Primary Flash Memory (8 uniform sectors) s 256Kbit Secondary EEPROM (4 uniform sectors) s Up to 16Kbit SRAM s Over 3,000 Gates of PLD: DPLD and CPLD s 27 Reconfigurable I/O ports s Enhanced JTAG Serial Port s Programmable power management s High Endurance: - 100,000 Erase/Write Cycles of Flash Memory - 10,000 Erase/Write Cycles of EEPROM - 1,000 Erase/Write Cycles of PLD Figure 1. Packages PQFP52 (T) PLCC52 (K) January 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/3 Revision A Flash PSD PSD813F1-A Flash In-System-Programmable Microcontroller Peripherals Table of Contents 1.0 Introduction ...........................................................................................................................................................1 2.0 Key Features ........................................................................................................................................................2 PSD813F1 Block Diagram .............................................................................................................................4 3.0 General Information ..............................................................................................................................................5 4.0 PSD813F1 Family.................................................................................................................................................5 5.0 PSD813F1 Architectural Overview .......................................................................................................................6 5.1 Memory........................................................................................................................