PSD813F1
FEATURES
SUMMARY s DUAL BANK FLASH MEMORIES
- 1 Mbit of Primary Flash Memory (8 Uniform Sectors)
- 256 Kbit Secondary EEPROM (4 Uniform Sectors)
- Concurrent operation: read from one memory while erasing and writing the other s 16 Kbit SRAM (BATTERY-BACKED) s PLD WITH MACROCELLS
- Over 3,000 Gates Of PLD: DPLD and CPLD
- DPLD
- User-defined Internal chip-select decoding
- CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs) s 27 RECONFIGURABLE I/Os
- 27 individually configurable I/O port pins that can be used for the following functions:
MCU I/Os;
PLD I/Os;
Latched MCU address output; and
Special function I/Os.
Note: 16 of the I/O ports may be configured as open-drain outputs. s ENHANCED JTAG SERIAL PORT
- Built-in JTAG-pliant serial port allows full-chip In-System Programmability (ISP)
- Efficient manufacturing allows for easy product testing and programming s PAGE REGISTER
- Internal page register that can be used to expand the microcontroller address space by a...
