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PSD813F1 - Flash In-System Programmable Peripherals

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PSD813F1 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V FEATURES SUMMARY s DUAL BANK FLASH MEMORIES – 1 Mbit of Primary Flash Memory (8 Uniform Sectors) – 256 Kbit Secondary EEPROM (4 Uniform Sectors) – Concurrent operation: read from one memory while erasing and writing the other s 16 Kbit SRAM (BATTERY-BACKED) s PLD WITH MACROCELLS – Over 3,000 Gates Of PLD: DPLD and CPLD – DPLD - User-defined Internal chip-select decoding – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs) s 27 RECONFIGURABLE I/Os – 27 individually configurable I/O port pins that can be used for the following functions: MCU I/Os; PLD I/Os; Latched MCU address output; and Special function I/Os. Note: 16 of the I/O ports may be configured as open-drain outputs.
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