PSD813F1 Overview
6 In-System Programming (ISP) via JTAG . 6 In-Application Programming (IAP) . 10 PSD ARCHITECTURAL OVERVIEW.
PSD813F1 Key Features
- 1 Mbit of Primary Flash Memory (8 Uniform Sectors)
- 256 Kbit Secondary EEPROM (4 Uniform Sectors)
- Concurrent operation: read from one memory while erasing and writing the other
- Over 3,000 Gates Of PLD: DPLD and CPLD
- User-defined Internal chip-select decoding
- CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
- 27 individually configurable I/O port pins that can be used for the following functions
- Built-in JTAG-pliant serial port allows full-chip In-System Programmability (ISP)
- Efficient manufacturing allows for easy product testing and programming
- Internal page register that can be used to expand the microcontroller address space by a factor of 256