PSD813F1V
Key Features
- DUAL BANK FLASH MEMORIES
- 256 Kbit Secondary EEPROM (4 Uniform t(sSectors)
- Concurrent operation: read from one
- 16 Kbit SRAM P t(s
- PLD WITH MACROCELLS te c
- Over 3,000 Gates Of PLD: DPLD and le uCPLD d
- DPLD - User-defined Internal chip-select so rodecoding b P
- CPLD with 16 Output Macrocells (OMCs) - O teand 24 Input Macrocells (IMCs)
- 27 RECONFIGURABLE I/Os
- ENHANCED JTAG SERIAL PORT
