PSD813F1V Description
10 PSD ARCHITECTURAL OVERVIEW.
PSD813F1V Key Features
- DUAL BANK FLASH MEMORIES
- 1 Mbit of Primary Flash Memory (8
- Concurrent operation: read from one
- User-defined Internal chip-select so rodecoding b P- CPLD with 16 Output Macrocells (OMCs)
- O teand 24 Input Macrocells (IMCs)
- 27 RECONFIGURABLE I/Os
- Built-in JTAG-pliant serial port allows b Pfull-chip In-System Programmability (ISP)
- HIGH ENDURANCE
- 100,000 Erase/WRITE Cycles of Flash Memory
- 10,000 Erase/WRITE Cycles of EEPROM