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STSMIA832 Datasheet standard mobile imaging architecture (SMIA) decoder deserializer

Manufacturer: STMicroelectronics

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General Description

The STSMIA832 receiver converts the subLVDS clock/datastream (up to 650 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/LVTTL.

The device recognizes the SMIA 32 bit start of frame (SOF), end of frame (EOF), start of line (SOL) and end of line (EOL) sequences to generate the H-SYNC and V-SYNC signals.

Output LVTTL clock (up to 82 MHz) is transmitted in parallel with data.

Overview

www.DataSheet4U.com STSMIA832 1.8V/2.8V High speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer Feature summary s Sub-low voltage differential signaling inputs: VID = 100mV MIN.

with RT = 100Ω, CL = 10pF High signaling rate: fIN = 650 Mbps MAX (D+,D-,STRB+,STRB-) fOUT = 82 MHz MAX (CLK) fOUT = 82 Mbps MAX (for each data line D1-D8) Very high speed strobe to clock: tpLH~tpHL=5.2ns (TYP) at VDD=2.8V; VL=1.8V Operating voltage range: VDD(OPR) = 2.65V to 3.6V VL(OPR) =1.65V to 1.95V Symmetrical output impedance (D1-D8, HSYNC, V-SYNC, CLK): IIOHI=IOL=4mA (MIN) at VDD=2.65V;VL=1.8V Low power dissipation (DISABLED: EN=Gnd): ISOFF = IDD + IL = 10 µA (Max) SMIA specification compliant CLASS 0 and CLASS 1,2 supported (config by CLASS_SEL) CMOS logic input threshold (EN, SYNC_SEL, CLASS_SEL): VIL = 0.3xVL; VL = 1.65V to 1.95V VIH = 0.7xVL; VL = 1.65V to 1.95V 3.

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