Click to expand full text
S T M9433
S amHop Microelectronics C orp.
P reliminary May.21, 2004
P -C hannel E nhancement Mode Field E ffect Transistor
P R ODUC T S UMMAR Y
V DS S
-18V
F E AT UR E S
( m W ) Max
ID
-5A
R DS (ON)
S uper high dense cell design for low R DS (ON ).
50 @ V G S = -4.5V 80 @ V G S = -2.5V
R ugged and reliable. S urface Mount P ackage.
D
8
D
7
D
6
D
5
S O-8 1
1 2 3 4
S
S
S
G
ABS OLUTE MAXIMUM R ATINGS (T A=25 C unless otherwise noted)
P arameter Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous a @ T J =125 C b -P ulsed Drain-S ource Diode Forward C urrent a Maximum P ower Dissipation a Operating Junction and S torage Temperature R ange S ymbol V DS V GS ID IDM IS PD T J , T S TG Limit 18 12 -5 -12.5 -1.7 2.
STM9433 Datasheet
