K4S561632C Datasheet - Samsung

K4S561632C 256Mbit SDRAM

The K4S561632C is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock.

www.DataSheet4U.com K4S561632C CMOS SDRAM 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL Revision 0.4 Sept. 2001 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.4 Sept. 2001 DataSheet 4 U .com www.DataSheet4U.com K4S561632C Revision History Revision 0.1 (Feb. 15, 2001) Added DC charcteristics. CMOS SDRAM Revision 0.2 (Mar. 06, 2001) Deleted "Preliminary" Changed DC charcteristics Revision.

K4S561632C Features

* JEDEC standard 3.3V power supply

* LVTTL compatible with multiplexed address

* Four banks operation

* MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)

* All inputs are

K4S561632C Datasheet (226.17 KB)