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KM736V787 - 128Kx36 Synchronous SRAM

General Description

The KM736V787 is 4,718,592 bits Synchronous Static Random Access Memory designed to support zero wait state performance for advanced Pentium/Power PC based system.

And with CS1 high, ADSP is blocked to control signals.

It can be organized as 128K words of 36 bits.

Key Features

  • Synchronous Operation.
  • On-Chip Address Counter.
  • Write Self-Timed Cycle.
  • On-Chip Address and Control Registers.
  • VDD= 3.3V+0.3V/-0.165V Power Supply.
  • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
  • 5V Tolerant Inputs except I/O Pins.
  • Byte Writable Function.
  • Global Write Enable Controls a full bus-width write.
  • Power Down State via ZZ Signal.
  • Asynchronou.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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KM736V787 Document Title 128Kx36-Bit Synchronous Burst SRAM 128Kx36 Synchronous SRAM Revision History Rev. No. 0.0 0.1 History Initial draft Modify power down cycle timing & Interleaved read timing, Insert Note 4 at AC timing characteristics. Change ISB1 value from 10mA to 30mA. Change ISB2 value from 10mA to 20mA. Change Undershoot spec from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2) Add Overshoot spec 4.6V((pulse width≤tCYC/2) Change VIH max from 5.5V to VDD+0.5V Change ISB2 value from 20mA to 30mA. Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V. Final spec Release Add VDDQ Supply voltage( 2.5V ) Draft Date May. 15. 1997 Feb. 11. 1998 Remark Preliminary Preliminary 0.2 April. 14. 1998 Preliminary 0.3 May. 13. 1998 Preliminary 1.0 2.0 May. 15.