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K4S510732B Datasheet Stacked 512Mbit SDRAM

Manufacturer: Samsung Semiconductor

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General Description

The K4S510732B is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 8 bits, fabricated with SAMSUNG's high performance CMOS technology.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Overview

Preliminary K4S510732B CMOS SDRAM Stacked 512Mbit SDRAM 16M x 8bit x 4 Banks Synchronous DRAM LVTTL www.DataSheet4U.com Revision 0.0 Feb.

2001 * Samsung Electronics reserves the right to change products or specification without Rev.

0.0 Feb.2001 Preliminary K4S510732B CMOS SDRAM Revision 0.0 (Feb., 2001) Rev.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (8K Cycle.

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