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K4S561632E-NCL75 Datasheet SDRAM 256Mb E-die

Manufacturer: Samsung Semiconductor

Download the K4S561632E-NCL75 datasheet PDF. This datasheet also includes the K4S560432E-NC variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (K4S560432E-NC_Samsungsemiconductor.pdf) that lists specifications for multiple related part numbers.

General Description

The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Overview

SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM 256Mb E-die SDRAM Specification 54pin sTSOP-II Revision 1.0 August.

2003 * Samsung Electronics reserves the right to change products or specification without notice.

Rev.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM (x4,x8) & L(U)DQM (x16) for masking.
  • Auto & self refresh.
  • 64ms.