pnp/npn epitaxial planar silicon transistors.
* Adoption of FBET process.
* High breakdown voltage : VCEO=(
–)50V.
* Large current capacitiy and high fT.
* Very small-sized package perm.
Features
* Adoption of FBET process.
* High breakdown voltage : VCEO=(
–)50V.
* Large curren.
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