Datasheet4U Logo Datasheet4U.com

THC63LVD104C - 112MHz 30Bits COLOR LVDS Receiver

Description

The THC63LVD104C receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions.

Features

  • Wide dot clock range: 8-112MHz suited for NTSC, VGA, SVGA, XGA, and SXGA.
  • PLL requires no external components.
  • 50% output clock duty cycle.
  • TTL clock edge programmable.
  • Power down mode.
  • Low power single 3.3V CMOS design.
  • 64pin TQFP.
  • Backward compatible with THC63LVDF64x (.

📥 Download Datasheet

Datasheet Details

Part number THC63LVD104C
Manufacturer THine Electronics
File Size 116.19 KB
Description 112MHz 30Bits COLOR LVDS Receiver
Datasheet download datasheet THC63LVD104C Datasheet

📁 Similar Datasheet

  • THC63LVD1027 - Dual Link LVDS Repeater (CEL)
  • THC63LVD827 - Low Power / Small Package / 24Bit Color LVDS Transmitter (THine)
  • THC63LVDF84C - 24bit Color LVDS Receiver (CEL)
  • THC697 - NPN Transistors (Allegro Microsystems)
  • THC699 - NPN Transistors (Allegro Microsystems)
  • THC1420 - NPN Transistors (Allegro Microsystems)
  • THC1566 - NPN Transistors (Allegro Microsystems)
  • THC1613 - NPN Transistors (Allegro Microsystems)
  • THC1711 - NPN Transistors (Allegro Microsystems)
  • THC2017 - NPN Transistors (Allegro Microsystems)
Other Datasheets by THine Electronics

Full PDF Text Transcription

Click to expand full text
THC63LVD104C_Rev.2.1_E THC63LVD104C 112MHz 30Bits COLOR LVDS Receiver General Description The THC63LVD104C receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104C converts the LVDS data streams back into 35bits of CMOS/TTL data with the choice of the rising edge or falling edge clock for the convenience with a variety of LCD panel controllers.At a transmit clock frequency of 112MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC,DE,CNTL1,CNTL2) are transmitted at an effective rate of 784Mbps per LVDS channel.Using a 112MHz clock, the data throughput is 490Mbytes per second.
Published: |