Description
The THC63LVDM63A transmitter converts 21 bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream.
A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.
Features
- 21:3 Data channel compression at up to 223 Megabytes per sec throughput Wide Frequency Range: 20 - 85 MHz suited for VGA,SVGA,XGA and SXGA Narrow bus (8 lines) reduces cable size 345mV swing LVDS devices for Low EMI Supports Spread Spectrum Clock Generator On chip Input Jitter Filtering PLL requires No External Components Single 3.3V supply with 110mW(TYP) Low Power CMOS Design Power-Down Mode Low profile 48 Lead TSSOP Package Clock Edge Programmable for Transmitter Improved Replacement for the.