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Toshiba Electronic Components Datasheet

TC358766XBG Datasheet

Mobile Peripheral

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TC358766XBG
CMOS Digital Integrated Circuit Silicon Monolithic
TC358766XBG
Mobile Peripheral Devices
Overview
The DSI/DPI to DisplayPortTM converter TC358766XBG is a bridge
device that enables video streaming from a Host (application or
baseband processor) over MIPI® DSI or DPI link to drive
DisplayPortTM display panels.
TC358766XBG
P-VFBGA120-0606-0.50AZ
Weight: 62mg (Typ.)
Features
● Translates MIPI® DSI/DPI Link video stream from
Host to DisplayPortTM Link data to external display
devices.
● The inputs are driven by a DSI Host with 4-Data
Lanes, upto1 Gbps/lane or DPI Host with 16/18/24
bit interface upto154 MHz parallel clock.
● Supports HDCP Digital Content Protection version
1.3 (DisplayPortTM amendment Rev1.1).
● The output Interface consists of a DisplayPortTM Tx
with a 2-lane Main Link and AUX-Ch.
● Register Configuration: From DSI link, SPI or I2C
interface (only one of the SPI and I2C interfaces
can be active at any time).
● Internally generated H/VSync in DSI mode can be
muxed out to Host.
● Interrupt to host to inform any error status or status
needing attention from Host.
● Internal test pattern (color bar) generator for DP
o/p testing without any video (DSI/DPI) i/p.
● Debug/Test Port: I2C Slave
DSI Receiver: Supports one DSI Interface
between TC358766XBG and Host.
MIPI® DSI: v1.01 / MIPI® D-PHY: v0.90
Compliant.
Up to four (4) Data Lanes with Bi-direction
support on Data Lane 0.
Maximum speed at 1 Gbps/lane.
Supports Burst as well as Non-Burst Mode
Video Data.
- Video data packets are limited to one row per
Hsync period.
Supports video stream packets for video data
transmission.
Supports generic long packets for accessing the
chip’s register set.
Video input data formats:
- RGB-565, RGB-666 and RGB-888.
- New DSI V1.02 Data Type Support: 16-bit
YCbCr 422
Interlaced video mode is not supported.
DPI Receiver: Supports one DPI Interface
between TC358766XBG and Host.
Up to 16 / 18 / 24 bit parallel data interface.
Maximum speed at 154 MPs (MPixel per sec).
Video input data formats: RGB-565, RGB-666
and RGB-888.
Only Progressive mode supported.
Shutdown support (can be used in non-DPI
mode also).
DisplayPortTM Interface: Supports a
DisplayPortTM link from TC358766XBG to display
panels.
High speed serial bridge chip using VESA
DisplayPortTM 1.1a Standard.
Supports one dual-lane DisplayPortTM port for
high bandwidth applications
Supports up to two (2) single-lane ports for
connection to two DisplayPortTM panels.
Support 1.62 or 2.7 Gbps/lane data rate with
voltage swings @0.4, 0.6, 0.8 or 1.2V
Support of pre-emphasis levels of 0, 3.5dB and
6dB.
Supports Audio related Secondary Data Packets
AUX channel supported at 1 Mbps.
HPD support through GPIO[1:0] based
interrupts
Enhanced mode supported for HDCP content
protection.
Support HDCP encryption Version 1.3 with
DisplayPortTM amendment Revision 1.1. (on
DisplayPortTM0 in case two port configuration is
used)
Stream Policy Maker is assumed handled by the
Host (software/firmware).
- Start Link training in response to HPD & read
final Link training status
- Configure DP link for actual video streaming &
start video streaming
© 2014-2018
Toshiba Electronic Devices & Storage Corporation
1 / 22
2018-05-28
Rev. 1.1


Toshiba Electronic Components Datasheet

TC358766XBG Datasheet

Mobile Peripheral

No Preview Available !

TC358766XBG
Link Policy maker is assumed shared between
the Host and TC358766XBG chip.
- In auto_correction = 0 mode, control link training
- Initiate Display device capabilities read and
configure TC358766XBG accordingly.
Video timing generation as per panel
requirement.
SSCG with up to 30 kHz modulation to reduce
EMI.
Toshiba Magic Square algorithm – RGB666 18b
produces RGB888 24b like quality (with up to
16-million colors).
Built in PRBS7 Generator to test DisplayPortTM
Link.
RGB Parallel Output Interface:
RGB888 output mode (DisplayPortTM disabled)
with only DSI input supported in this mode
PCLK max = 100 MHz
Polarity control for PCLK, VSYNC, HSYNC &
DE.
I2C Interface:
I2C slave interface for chip register set access
enabled using a boot-strap option.
I2C compliant slave interface support for normal
(100 kHz) and fast mode (400 kHz).
SPI Interface:
SPI slave interface for chip register set access
enabled using a boot-strap option.
SPI interface support for up to 30 MHz
operation.
GPIO Interface:
2 bits of GPIO (shared with other digital logic).
Direction controllable by Host I2C accesses.
Clock Source:
DisplayPortTM clock source is from an external
clock input or clock from DSI interface (13, 26,
19.2 or 38.4 MHz) – generates all internal &
output clocks to interfacing display devices.
Built-in PLLs generate high-speed DisplayPortTM
link clock requiring no external components.
These PLLs are part of the DisplayPortTM PHY.
● Clock and power management support to achieve
low power states.
Possible modes of Operation: Supports six (6)
modes of operation:
MODE S21: TC358766XBG uses DisplayPortTM
Tx as single 2-lane DisplayPortTM link to
interface to single DisplayPortTM display device.
Video stream source is from MIPI® DSI Host.
MODE S22: TC358766XBG uses DisplayPortTM
Tx port as two independent 1-lane DisplayPortTM
links to interface to two (2) DisplayPortTM display
devices. Video stream source is from MIPI® DSI
Host. Same video stream can be displayed on
two display devices.
MODE P21: TC358766XBG uses DisplayPortTM
Tx as single 2-lane DisplayPortTM link to
interface to single DisplayPortTM display device.
Video stream source is from MIPI® DPI Host.
MODE P22: TC358766XBG uses DisplayPortTM
Tx port as two independent 1-lane DisplayPortTM
links to interface to two (2) DisplayPortTM display
devices. Video stream source is from MIPI® DPI
Host. Same video stream is displayed on two
display devices.
MODE SP22: TC358766XBG uses
DisplayPortTM Tx as two independent
DisplayPortTM output links (each single lane).
TC358766XBG routes the DSI input to one
DisplayPortTM Tx link and routes the DPI input to
the second DisplayPortTM Tx link.
MODE S2P: TC358766XBG uses only Parallel
output port and disables DisplayPortTM Tx to
interface to single RGB display device. Video
stream source is from MIPI® DSI Host.
Power supply inputs
Core and MIPI® D-PHY: 1.2V ±0.06V
Digital I/O: 1.8V ±0.09V
DisplayPortTM: 1.8V ±0.09V
DisplayPortTM: 1.2V ±0.06V
Power Consumptions (based on estimations)
Power-down mode (DSI-Rx in ULPS, DP PHY &
PLLs disabled, clocks stopped):
- DSI Rx: 0.01 mW
- DP PHY: 2.34 mW
- PLL9:
0.01 mW
- Core:
0.96 mW
- Rest:
0.01 mW
Normal operation (1920 x 1080 resolution with
DSI-Rx in 4-lane @925 Mbps per lane, DP PHY
in dual lane link @2.7 Gbps per lane):
- DSI Rx: 21.79 mW
- DP PHY: 142.70 mW
- PLL9:
2.42 mW
- Core:
87.64 mW
- IOs:
1.68 mW
© 2014-2018
Toshiba Electronic Devices & Storage Corporation
2 / 22
2018-05-28
Rev. 1.1


Part Number TC358766XBG
Description Mobile Peripheral
Maker Toshiba
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