TC358771XBG
Overview
- DSI Receiver Configurable 1- up to 4-Data-Lane DSI Link with bi-directional support on Data Lane 0 Maximum bit rate of 1 Gbps/lane Video input data formats: - RGB565 16 bits per pixel - RGB666 18 bits per pixel - RGB666 loosely packed 24 bits per pixel - RGB888 24 bits per pixel Video frame size: - Up to 1600×1200 24-bit/pixel resolution to single-link LVDS display panel, limited by 135 MHz LVDS speed - Up to WUXGA resolutions (1920×1200 24-bit pixels) to dual-link LVDS display panel, limited by 4 Gbps DSI link speed Supports Video Stream packets for video data transmission. Supports generic long packets for accessing the chip's register set Supports the path for Host to control the on-chip I2C Master
- LVDS FPD Link Transmitter Supports single-link or dual-link Maximum pixel clock fr
