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TC551402J-30 - CMOS SRAM

Download the TC551402J-30 datasheet PDF. This datasheet also covers the TC551402J-20 variant, as both devices belong to the same cmos sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The TC551402J is a 4,194,304 bit high speed CMOS static random access memory that is configurable to an organization of either 4,194,304 words by 1 bit or 1,048,576 words by 4 bits when power is initially applied to the device.

The mode (x1/x4) is selected by the input level of pin 17 (81/84).

Key Features

  • low power dissipation when the SRAM is deselected using chip enable (CE), and has an output enable input (OE) for fast memory access. It is suitable for use in high speed.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC551402J-20-Toshiba.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Toshiba

Part Number Description
TC551402J-20 CMOS SRAM
TC5514AP (TC5514P/AP/APL) 1024 x 4-Bit CMOS Static RAM
TC5514APL (TC5514P/AP/APL) 1024 x 4-Bit CMOS Static RAM
TC5514P (TC5514P/AP/APL) 1024 x 4-Bit CMOS Static RAM
TC551001AFI-10 SILICON GATE CMOS STATIC RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TOSHIBA 11:551402J-20/25/30 4,194,304 WORD x 1 BIT/1,048,576 WORD x 4 BIT CMOS STATIC RAM Description The TC551402J is a 4,194,304 bit high speed CMOS static random access memory that is configurable to an organization of either 4,194,304 words by 1 bit or 1,048,576 words by 4 bits when power is initially applied to the device. The mode (x1/x4) is selected by the input level of pin 17 (81/84). The TC551402J operates from a single 5V supply. Toshiba's advanced CMOS technology and circuit design enable high speed operation. The TC551402J features low power dissipation when the SRAM is deselected using chip enable (CE), and has an output enable input (OE) for fast memory access. It is suitable for use in high speed applications such as cache memory, high speed storage, and main memory.