TC55BS8128J Datasheet PDF (128K x 8-Bit Synchronous Static RAM)

TC55BS8128J - 128K x 8-Bit Synchronous Static RAM

Description

The TC55BS8128J is a 1,048,576 bit synchronous static random access memory fabricated using BiCMOS technology and organized as 131,072 words by 8 bits.

The TC55BS8128J is similar to the TC55BS8125J but has separate data inputs and outputs and a write-cycle pass-through feature.

Features

Fast cycle time - TC55BS8128J-10 10ns (max. ) - TC55BS8128J-12 12ns (max. ).
Fast clock access time - TC55BS8128J-10 5ns (max. ) - TC55BS8128J-12 6ns (max. ).
Input and output registers for synchronous operation.
Data pass-through for write cycles.
Single power supply: 5V±10%.
Separate data inputs and outputs.
Package: JEDEC standard pinout - 40-pin, 400mil SOJ: SOJ40-P-400 Pin Names AO - A16 DO - 07 00-07 ClK CE WE V DD GND Address I.

Datasheet Details

Part number	TC55BS8128J
Manufacturer	Toshiba
File Size	153.64 KB
Description	128K x 8-Bit Synchronous Static RAM
Datasheet	TC55BS8128J Datasheet
Additional preview pages of the TC55BS8128J datasheet.

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Full PDF Text Transcription

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TOSHIBA 131,072 WORD x 8 BIT SYNCHRONOUS STATIC RAM with Input Registers, Output Registers and Pass-Through Feature 1l:55~128J-I0/12 PRELIMINARY Description The TC55BS8128J is a 1,048,576 bit synchronous static random access memory fabricated using BiCMOS technology and organized as 131,072 words by 8 bits. The TC55BS8128J is similar to the TC55BS8125J but has separate data inputs and outputs and a write-cycle pass-through feature. Designed for pipelined architectures, this device has internal input and output registers which latch on the positive edge of an external clock (ClK). All address; data, and control signals are latched. The setup and hold times for the inputs are 2ns and 1ns respectively.

Published: Jun 8, 2006 |