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TC55V1864FT-10 - 18-Bit CMOS SRAM

Download the TC55V1864FT-10 datasheet PDF. This datasheet also covers the TC55V1864J-10 variant, as both devices belong to the same 18-bit cmos sram family and are provided as variant models within a single manufacturer datasheet.

Description

The TC55V1864J/FT is a 1,179,648 bit high speed CMOS static random access memory organized as 65,536 words by 18 bits and operated from a single 3.3V supply.

Toshiba's advanced CMOS technology and circuit design enable hJ9!:l speed operation.

Features

  • low power dissipation when the device is deselected using chip enable (CE), and has an output enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls. The TC55V1864J/FT is suitable for use in high speed.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC55V1864J-10-Toshiba.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TOSHIBA 1l:55T1864J/F1l-10/12/15 SILICON GATE CMOS PRELIMINARY 65,536 WORD x 18 BIT CMOS STATIC RAM Description The TC55V1864J/FT is a 1,179,648 bit high speed CMOS static random access memory organized as 65,536 words by 18 bits and operated from a single 3.3V supply. Toshiba's advanced CMOS technology and circuit design enable hJ9!:l speed operation. The TC55V1864J/FT features low power dissipation when the device is deselected using chip enable (CE), and has an output enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls. The TC55V1864J/FT is suitable for use in high speed applications such as cache memory and high speed storage. All inputs and outputs are LVTTL compatible.
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