TC74HC40105AP
Features
- High speed: fmax 25 MHz (typ.) at VCC = 5 V
- Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
- High noise immunity: VNIH = VNIL = 28% VCC (min)
- Output drive capability: 10 LSTTL loads for DIR, DOR
15 LSTTL loads for Q0 to Q3
- Symmetrical output impedance: |IOH| = IOL = 4 m A (min) for DIR, DOR |IOH| = IOL = 6 m A (min) for Q0 to Q3
- Balanced propagation delays: tp LH ∼- tp HL
- Wide operating voltage range: VCC (opr) = 2 to 6 V
TC74HC40105AP TC74HC40105AF
Weight DIP16-P-300-2.54A SOP16-P-300-1.27A
: 1.00 g (typ.) : 0.18 g (typ.)
Start of mercial production
1986-05
2014-03-01
Pin Assignment IEC Logic Symbol System Diagram
TC74HC40105AP/AF
2014-03-01
Timing Chart
TC74HC40105AP/AF
Z: High impedance
Block Diagram
2014-03-01
TC74HC40105AP/AF
Functional Description
(1) Writing data Data can be written into the FIFO whenever DIR is high and a low to high transition occurs on the
SI pin. DIR will toggle momentarily until the data has been transferred to...
