TH50VSF2581AASB Description
The TH50VSF2580/2581AASB is a mixed multi-chip package containing a 4,194,304-bit full CMOS SRAM and a 33,554,432-bit flash memory. The CIOS and CIOF inputs can be used to select the optimal memory configuration. The power supply for the TH50VSF2580/2581AASB can range from 2.7 V to 3.6.
TH50VSF2581AASB Key Features
- Data retention supply voltage VCCs = 1.5 V~3.6 V
- Current consumption Operating: 45 mA maximum (CMOS level) Standby: 7 µA maximum (SRAM CMOS level) Standby: 10 µA maximum
- Block erase architecture for flash memory 8 blocks of 8 Kbytes 63 blocks of 64 Kbytes
- Organization
- CIOF = VCC, CIOS = VCC (×16, ×16)
- TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devic