Datasheet4U Logo Datasheet4U.com

UR5596 - DDR TERMINATION REGULATOR

General Description

The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM.

It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme.

Key Features

  • S.
  • Source and sink current.
  • Low output voltage offset.
  • No external resistors required.
  • Linear topology.
  • Suspend To Ram (STR) functionality.
  • Low external component count.
  • Thermal shutdown protection CMOS IC www. unisonic. com. tw Copyright © 2022 Unisonic Technologies Co. , Ltd 1 of 12 QW-R502-045.E UR5596.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
UR5HC418 AT / PS/2 - Compatible Keyboard Encoder Semtech Corporation
UR5HC418-FB AT / PS/2 - Compatible Keyboard Encoder Semtech Corporation
UR5HC418-FN AT / PS/2 - Compatible Keyboard Encoder Semtech Corporation
UR5HC418-P AT / PS/2 - Compatible Keyboard Encoder Semtech Corporation
UR5HC703-600-FG USAR SerialCoderTM Low-Power Keyboard Encoder interfaces RS-232 Semtech Corporation

Other Datasheets by Unisonic Technologies

Part Number Description
UR5595 DDR TERMINATION REGULATOR
UR5512 2A DDR BUS TERMINATION REGULATOR
UR5515 1.5A/3A BUS TERMINATION REGULATOR
UR5516 3A BUS TERMINATION REGULATOR
UR5516A 3A BUS TERMINATION REGULATOR

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
UNISONIC TECHNOLOGIES CO., LTD UR5596 DDR TERMINATION REGULATOR  DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The UTC UR5596 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. Besides, an active low shutdown (SHDN) pin provides Suspend To RAM (STR) functionality.