UR5596
Overview
The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme.
- Source and sink current * Low output voltage offset * No external resistors required * Linear topology * Suspend To Ram (STR) functionality * Low external component count * Thermal shutdown protection CMOS IC Copyright © 2022 Unisonic Technologies Co., Ltd 1 of 12
