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UR5596 - DDR TERMINATION REGULATOR

Description

The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM.

It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme.

Features

  • S.
  • Source and sink current.
  • Low output voltage offset.
  • No external resistors required.
  • Linear topology.
  • Suspend To Ram (STR) functionality.
  • Low external component count.
  • Thermal shutdown protection CMOS IC www. unisonic. com. tw Copyright © 2022 Unisonic Technologies Co. , Ltd 1 of 12 QW-R502-045.E UR5596.

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Full PDF Text Transcription

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UNISONIC TECHNOLOGIES CO., LTD UR5596 DDR TERMINATION REGULATOR  DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The UTC UR5596 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. Besides, an active low shutdown (SHDN) pin provides Suspend To RAM (STR) functionality.
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