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VIS
Description
Preliminary
VG36128401A VG36128801A VG36128161A
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 8,388,608 - word x 4 -bit x 4 - bank, 4,194,304 - word x 8 - bit x 4 - bank, or 2,097,152 - word x 16 - bit x 4 - bank. These various organizations provide wide choice for different applications. It is designed with the state-of-the-art technology to meet standard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the performance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.
Features
• Single 3.3V ( ± 0.3V) power supply • High speed clock cycle time : 7.
VG36128161A Datasheet
