W3E232M16S-XSTX - 2x32Mx16bit DDR SDRAM

Datasheet Summary

Description

The 2x32Mx16 (1Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 2 chips containing 536,870,912 bits.

Each chip is internally configured as a quad-bank DRAM.

The 2x32Mx16 DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation.

Features

Double-data-rate architecture; two data transfers per clock cycle Data rate = 200, 266, 333, 400 Mbs Package:.
66pin TSOP II package 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs(CK and CK#) DLL aligns DQ and DQS transition with CK MRS cycle with address key programs.
Read latency : 2, 2.5 , 3 (Clock).
Burst length (2, 4, or 8).
Burst type (sequential & interleave) Auto & Self refresh Modes www. DataSheet4U. com W3E232M16S-.

White Electronic

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Datasheet Details

Part number	W3E232M16S-XSTX
Manufacturer	White Electronic
File Size	866.98 KB
Description	2x32Mx16bit DDR SDRAM
Datasheet	W3E232M16S-XSTX Datasheet
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White Electronic Designs 2x32Mx16bit DDR SDRAM FEATURES Double-data-rate architecture; two data transfers per clock cycle Data rate = 200, 266, 333, 400 Mbs Package: • 66pin TSOP II package 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs(CK and CK#) DLL aligns DQ and DQS transition with CK MRS cycle with address key programs • Read latency : 2, 2.5 , 3 (Clock) • Burst length (2, 4, or 8) • Burst type (sequential & interleave) Auto & Self refresh Modes www.DataSheet4U.com W3E232M16S-XSTX PRELIMINARY* Bidirectional data strobe (DQS) transmitted/ received with data, i.e.

Published: Jun 8, 2007 |