W3E32M72SR-XSBX
FEATURES
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- Registered for enhanced performance of bus speeds of 200, 250, 266Mb/s Package:
- 208 Plastic Ball Grid Array (PBGA), 16 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 patible) Differential clock inputs (CK and CK#) mands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) pins for masking write data (one per byte) Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes mercial, Industrial and Military Temperature Ranges Organized as 32M x 72 Weight: W3E32M72SR-XSBX
- 2.5 grams typical
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- W3E32M72SR-XSBX
BENEFITS
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