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W942508CH Datasheet Preview

W942508CH Datasheet

DDR SDRAM

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W942508CH
8M × 4 BANKS × 8 BIT DDR SDRAM
Table of Contents-
1. GENERAL DESCRIPTION .................................................................................................. 3
2. FEATURES .......................................................................................................................... 3
3. KEY PARAMETERS ............................................................................................................ 4
4. PIN CONFIGURATION ........................................................................................................ 5
5. PIN DESCRIPTION.............................................................................................................. 6
6. BLOCK DIAGRAM ............................................................................................................... 7
7. ELECTRICAL CHARACTERISTICS .................................................................................... 8
7.1 Absolute Maximum Ratings ................................................................................................. 8
7.2 Recommended DC Operating Conditions............................................................................ 8
7.3 Capacitance ......................................................................................................................... 9
7.4 Leakage and Output Buffer Characteristics ......................................................................... 9
7.5 DC Characteristics ............................................................................................................. 10
7.6 AC Characteristics and Operating Condition ..................................................................... 11
7.7 AC Test Conditions ............................................................................................................ 13
8. Operation Mode ................................................................................................................. 15
8.1 Simplified Truth Table ........................................................................................................ 15
8.2 Function Truth Table .......................................................................................................... 16
8.3 Function Truth Table for CKE ............................................................................................ 19
8.4 Simplified State Diagram.................................................................................................... 20
9. FUNCTIONAL DESCRIPTION........................................................................................... 21
9.1 Power Up Sequence .......................................................................................................... 21
9.2 Command Function............................................................................................................ 21
9.3 Read Operation.................................................................................................................. 24
9.4 Write Operation .................................................................................................................. 24
9.5 Precharge........................................................................................................................... 24
9.6 Burst Termination............................................................................................................... 25
9.7 Refresh Operation.............................................................................................................. 25
9.8 Power Down Mode............................................................................................................. 25
9.9 Mode Register Operation ................................................................................................... 25
10. TIMING WAVEFORMS ............................................................................................................. 29
10.1 Command Input Timing...................................................................................................... 29
10.2 Timing of the CLK Signals.................................................................................................. 29
10.3 Read Timing (Burst Length = 4) ......................................................................................... 30
10.4 Write Timing (Burst Length = 4) ......................................................................................... 31
10.5 DM, DATA MASK (W942508CH/W942504CH) ................................................................. 32
Publication Release Date: May 21, 2003
- 1 - Revision A3




Winbond

W942508CH Datasheet Preview

W942508CH Datasheet

DDR SDRAM

No Preview Available !

W942508CH
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
10.19
10.20
10.21
10.22
10.23
10.24
10.25
10.26
DM, DATA MASK (W942516CH)....................................................................................... 32
Mode Register Set (MRS) Timing ...................................................................................... 33
Extend Mode Register Set (EMRS) Timing........................................................................ 34
Auto Precharge Timing (Read Cycle, CL = 2).................................................................... 35
Auto Precharge Timing (Write Cycle)................................................................................. 37
Read Interrupted by Read (CL = 2, BL = 2, 4, 8) ............................................................... 38
Burst Read Stop (BL = 8) ................................................................................................... 38
Read Interrupted by Write & BST (BL = 8)......................................................................... 39
Read Interrupted by Precharge (BL = 8) ............................................................................ 39
Write Interrupted by Write (BL = 2, 4, 8) ............................................................................ 40
Write Interrupted by Read (CL = 2, BL = 8) ....................................................................... 40
Write Interrupted by Read (CL = 2.5, BL = 4) .................................................................... 41
Write Interrupted by Precharge (BL = 8) ............................................................................ 41
2 Bank Interleave Read Operation (CL = 2, BL = 2) .......................................................... 42
2 Bank Interleave Read Operation (CL = 2, BL = 4) .......................................................... 42
4 Bank Interleave Read Operation (CL = 2, BL = 2) .......................................................... 43
4 Bank Interleave Read Operation (CL = 2, BL = 4) .......................................................... 43
Auto Refresh Cycle ............................................................................................................ 44
Active Power Down Mode Entry and Exit Timing............................................................... 44
Precharged Power Down Mode Entry and Exit Timing ...................................................... 44
Self Refresh Entry and Exit Timing .................................................................................... 45
11. PACKAGE DIMENSION ........................................................................................................... 46
11.1 TSOP 66l – 400 mil ............................................................................................................ 46
12. REVISION HISTORY ................................................................................................................ 47
-2-


Part Number W942508CH
Description DDR SDRAM
Maker Winbond
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