W986408CH
Description
W986408CH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 2M words x 4 banks x 8 bits. Using pipelined architecture and 0.20um process technology, W986408CH delivers a data bandwidth of up to 133M ( 75) bytes per second.
Key Features
- 3.3V ± 0.3V power supply Up to 133MHz clock frequency 2,097,152 words x 4 banks x 8 bits organization Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8 , and full page Burst read, Single Writes Mode Byte data controlled by DQM Power-Down Mode Auto-Precharge and controlled precharge 4k refresh cycles / 64ms Interface: LVTTL Package: TSOP II 54 pin, 400 mil - 0.80
