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W986408CH Datasheet Preview

W986408CH Datasheet

2M x 8BIT x 4 BANKS SDRAM

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W986408CH
Features
3.3V ± 0.3V power supply
Up to 133MHz clock frequency
2,097,152 words x 4 banks x 8 bits organization
Auto Refresh and Self Refresh
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8 , and full page
Burst read, Single Writes Mode
Byte data controlled by DQM
Power-Down Mode
Auto-Precharge and controlled precharge
4k refresh cycles / 64ms
Interface: LVTTL
Package: TSOP II 54 pin, 400 mil - 0.80
2M x 8 bit x 4 Banks SDRAM
General Description
W986408CH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 2M words x 4 banks x
8 bits. Using pipelined architecture and 0.20um process technology, W986408CH delivers a data bandwidth of up to 133M ( -
75) bytes per second. To fully comply to the personal computer industrial standard, W986408CH is sorted into two speed
grades: -75 and -8H. The -75 is compliant to the PC133 specitication, The -8H is compliant to the PC100/CL2 specification
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of
1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated
by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock
cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst
to maximize its performance. W986408CH is ideal for main memory in high performance applications.
Key Parameters
Symbol
Description
tCK Clock Cycle Time
tAC Access Time from CLK
tRP Precharge to Active Command
tRCD Active to Read/Write Command
ICC1 Operation Current ( Single bank )
ICC4 Burst Operation Current
ICC6 Self-Refresh Current
min/max
min
max
min
min
max
max
max
-75 (PC133)
7.5ns
5.4ns
20ns
20ns
65mA
115mA
1mA
-8H (PC100)
8ns
6ns
20ns
20ns
60mA
110mA
1mA
Revision 1.0
Publication Release Date: March, 1999
-1-




Winbond

W986408CH Datasheet Preview

W986408CH Datasheet

2M x 8BIT x 4 BANKS SDRAM

No Preview Available !

BLOCK DIAGRAM
CLK
CKE
CLOCK
BUFFER
CS
RAS
CAS
WE
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10
MODE
A0 REGISTER
ADDRESS
BUFFER
A9
A11
BS0
BS1
REFRESH
COUNTER
COLUMN
COUNTER
W986408CH
2M x 8 bit x 4 Banks SDRAM
COLUMN DECODER
CELL ARRAY
BANK #0
SENSE AMPLIFIER
DATA CONTROL
CIRCUIT
COLUMN DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
DMn
DQ
BUFFER
DQ0
DQ7
DQM
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
NOTE:
The cell array configuration is 4096 * 512 * 8.
Revision 1.0
Publication Release Date: March, 1999
-2-


Part Number W986408CH
Description 2M x 8BIT x 4 BANKS SDRAM
Maker Winbond
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