900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






Winbond

W986432AH Datasheet Preview

W986432AH Datasheet

512K x 4 BANKS x 32-BITS SDRAM

No Preview Available !

W986432AH
512K × 4 BANKS × 32 BITS SDRAM
GENERAL DESCRIPTION
W986432AH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words × 4 banks × 32 bits. Using pipelined architecture and 0.20 µm process technology,
W986432AH delivers a data bandwidth of up to 732M bytes per second (-55). For different
application, W986432AH is sorted into four speed grades: -55, -6, -7 and -8.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W986432AH is ideal for main memory in
high performance applications.
FEATURES
3.3V ±0.3V power supply
524288 words × 4 banks × 32 bits organization
Auto Refresh and Self Refresh
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Sequential and Interleave burst
Burst read, single write operation
Byte data controlled by DQM
Power-down Mode
Auto-precharge and controlled precharge
4K refresh cycles/64 mS
Interface: LVTTL
Packaged in 86-pin TSOP II, 400 mil - 0.50
PIN CONFIGURATION
Publication Release Date: December 1999
- 1 - Revision A1




Winbond

W986432AH Datasheet Preview

W986432AH Datasheet

512K x 4 BANKS x 32-BITS SDRAM

No Preview Available !

W986432AH
PIN DESCRIPTION
PIN NAME
A0A10
BS0, BS1
DQ0DQ31
CS
RAS
CAS
WE
DQM0
DQM3
CLK
CKE
VCC
VSS
VCCQ
VSSQ
NC
FUNCTION
DESCRIPTION
Address
Multiplexed pins for row and column address.
Row address: A0A10. Column address: A0A7.
A10 is sampled during a precharge command to determine if
all banks are to be precharged or bank selected by BS0, BS1.
Bank Select
Select bank to activate during row address latch time, or bank
to read/write during address latch time.
Data Input/
Output
Multiplexed pins for data output and input.
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Row Address
Strobe
Command input. When sampled at the rising edge of the
clock RAS , CAS and WE define the operation to be
executed.
Column Address Referred to RAS
Strobe
Write Enable
Referred to RAS
Input/output mask The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle, sampling
DQM high will block the write operation with zero latency.
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside DRAM.
Power (+3.3V) for Separated power from VCC, to improve DQ noise immunity.
I/O buffer
Ground for I/O
buffer
Separated ground from VSS, to improve DQ noise immunity.
No Connection No connection
-2-


Part Number W986432AH
Description 512K x 4 BANKS x 32-BITS SDRAM
Maker Winbond
PDF Download

W986432AH Datasheet PDF






Similar Datasheet

1 W986432AH 512K x 4 BANKS x 32-BITS SDRAM
Winbond





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy