W986432AH Datasheet | Winbond

DESCRIPTION W986432AH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words × 4 banks × 32 bits. Using pipelined architecture and 0.20 µm process technology, W986432AH delivers a data bandwidth of up to 732M bytes per second (-55). For different application, W986432AH is sorted into four speed grades: -55, -6, -7 and -8. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE mand. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W986432AH is ideal for main memory in high performance applications. FEATURES - 3.3V ±0.3V power supply - 524288 words × 4 banks × 32 bits organization - Auto Refresh and Self Refresh - CAS latency: 2 and 3 - Burst Length: 1, 2, 4, 8, and full page - Sequential and Interleave burst - Burst read, single write operation - Byte data controlled by DQM - Power-down Mode - Auto-precharge and controlled precharge - 4K refresh cycles/64 m S - Interface: LVTTL - Packaged in 86-pin TSOP II, 400 mil - 0.50 PIN CONFIGURATION Vss DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VCCQ DQ30 DQ29 VSSQ DQ28 DQ27 VCCQ DQ26 DQ25 VSSQ DQ24 VSS 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VCC 1 DQ0 2 VCCQ 3 DQ1 4 DQ2 5 VSSQ 6 DQ3 7 DQ4 8 VCCQ 9 DQ5 10 DQ6 11 VSSQ 12 DQ7 13 NC 14 VCC 15 DQM0 16 WE 17 CAS 18 RAS 19 CS 20 NC 21 BS0 22 BS1 23 A10/AP 24 A0 25 A1 26 A2 27...