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XCR3256XL Datasheet Preview

XCR3256XL Datasheet

256 Macrocell CPLD

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R XCR3256XL 256 Macrocell CPLD
DS013 (v1.2) May 3, 2000
0 14 Preliminary Product Specification
Features
• 7.5 ns pin-to-pin logic delays
• System frequencies up to 140 MHz
• 256 macrocells with 6,000 usable gates
• Available in small footprint packages
- 144-pin TQFP (116 user I/O pins)
- 208-pin PQFP (160 user I/O)
- 280-ball CS BGA (160 user I/O)
• Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five metal layer re-
programmable process
- FZP™ CMOS design technology
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 clocks available per logic block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per logic block
• Fast ISP programming times
• Port Enable pin for additional I/O
• 2.7V to 3.6V industrial grade voltage range
• Programmable slew rate control per output
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 16 logic blocks provide
6,000 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 140 MHz.
TotalCMOS™ Design Technique for
Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate
implementation allows Xilinx to offer CPLDs that are both
high performance and low power, breaking the paradigm
that to have low power, you must have low performance.
Refer to Figure 1 and Table 1 showing the ICC vs. Fre-
quency of our XCR3256XL TotalCMOS CPLD (data taken
with 16 up/down, loadable 16-bit counters at 3.3V, 25°C).
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners.
All specifications are subject to change without notice.
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1




Xilinx

XCR3256XL Datasheet Preview

XCR3256XL Datasheet

256 Macrocell CPLD

No Preview Available !

XCR3256XL 256 Macrocell CPLD
R
140
120
100
80
60
40
20
0
0
20 40
60 80 100 120 140
Frequency (MHz)
Figure 1: XCR3256XL Typical ICC vs. Frequency at VCC = 3.3V, 25°C
160
Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C
Frequency (MHz)
0
1 10 20 40 60 80 100 120 140
Typical ICC (mA) 0.02 0.91 8.87 17.7 34.8 51.5 68 84.2 100.1 116.6
DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol
Parameter
Test Conditions
Min.
Max. Unit
VOH
VOL
IIL
IIH
ICCSB
ICC
Output High voltage for 3.3V outputs
Output Low voltage for 3.3V outputs
Input leakage current
I/O High-Z leakage current
Standby current
Dynamic current(2,3)
IOH = 8 mA
IOL = 8 mA
VIN = GND or VCC
VIN = GND or VCC
VCC = 3.6V
f = 1 MHz
f = 50 MHz
2.4 - V
- 0.4 V
10 10 mA
10 10 mA
- 100 mA
- 2 mA
- 60 mA
CIN
CCLK
CI/O
Input pin capacitance(4)
Clock input capacitance(4)
I/O pin capacitance(4)
f = 1 MHz
f = 1 MHz
f = 1 MHz
- 8 pF
5 12 pF
- 10 pF
Notes:
1. See XPLA3 family data sheet (DS012) for recommended operating conditions.
2. See Table 1, Figure1 for typical values.
3. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and
unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
4. Typical values not tested.
2
www.xilinx.com
DS013 (v1.2) May 3, 2000
1-800-255-7778
Preliminary Product Specification


Part Number XCR3256XL
Description 256 Macrocell CPLD
Maker Xilinx
Total Page 10 Pages
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