XCR3512XL Key Features
- Lowest power 512 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 127 MHz 512 macrocells with 12,8
- 208-pin PQFP (180 user I/O)
- 256-ball FBGA (212 user I/O)
- 324-ball FBGA (260 user I/O) Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM process
- FZP™ CMOS design technology Advanced system features
- In-system programming
- Input registers