XCR3512XL Datasheet, Xilinx

*
*
*
*
* Lowest power 512 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 127 MHz 512 macrocells with 12,800 usable gates Avai.

The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 32 function blocks provide 12,800 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum.