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XCR3512XL - 512 Macrocell CPLD

Datasheet Summary

Description

The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.

A total of 32 function blocks provide 12,800 usable gates.

Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 127 MHz.

Features

  • Lowest power 512 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 127 MHz 512 macrocells with 12,800 usable gates Available in small footprint packages - 208-pin PQFP (180 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (260 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - FZP™ CMOS design technology.

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Datasheet Details

Part number XCR3512XL
Manufacturer Xilinx
File Size 141.92 KB
Description 512 Macrocell CPLD
Datasheet download datasheet XCR3512XL Datasheet
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0 R XCR3512XL: 512 Macrocell CPLD 0 14 DS081 (v1.2) September 4, 2001 Advance Product Specification Features • • • • • Lowest power 512 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 127 MHz 512 macrocells with 12,800 usable gates Available in small footprint packages - 208-pin PQFP (180 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (260 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - FZP™ CMOS design technology Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 clocks available per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.
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