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XQR2V1000 Datasheet

QPro Virtex-II 1.5V Radiation Hardened QML Platform FPGAs

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0
R QPro Virtex-II 1.5V Radiation
Hardened QML Platform FPGAs
DS124 (v1.1) January 8, 2004
0 0 Product Specification
Summary of Radiation Hardened QPro™ Virtex™-II Features
• Industry First Radiation Hardened Platform FPGA
Solution
• Guaranteed total ionizing dose to 200K Rad(si)
• Latch-up immune to LET > 160 MeV-cm2/mg
• SEU in GEO upsets < 1.5E-6 per device day
achievable with recommended redundancy
implementation
• Certified to MIL-PRF-38535 (Qualified Manufacturer
Listing)
• Guaranteed over the full military temperature range
(–55° C to +125° C)
• Ceramic and Plastic Wire-Bond and Flip-Chip Grid
Array Packages
• IP-Immersion Architecture
- Densities from 1M to 6M system gates
- 300+ MHz internal clock speed (Advance Data)
- 622+ Mb/s I/O (Advance Data)
• SelectRAM™ Memory Hierarchy
- 2.5 Mb of dual-port RAM in 18 Kbit block
SelectRAM resources
- Up to 1 Mb of distributed SelectRAM resources
• High-Performance Interfaces to External Memory
- DRAM interfaces
· SDR/DDR SDRAM
· Network FCRAM
· Reduced Latency DRAM
- SRAM interfaces
· SDR/DDR SRAM
· QDR SRAM
- CAM interfaces
• Arithmetic Functions
- Dedicated 18-bit x 18-bit multiplier blocks
- Fast look-ahead carry logic chains
• Flexible Logic Resources
- Up to 67,584 internal registers/latches with Clock
Enable
- Up to 67,584 look-up tables (LUTs) or cascadable
16-bit shift registers
- Wide multiplexers and wide-input function support
- Horizontal cascade chain and sum-of-products
support
- Internal 3-state busing
• High-Performance Clock Management Circuitry
- Up to 12 DCM (Digital Clock Manager) modules
· Precise clock de-skew
· Flexible frequency synthesis
· High-resolution phase shifting
- 16 global clock multiplexer buffers
• Active Interconnect Technology
- Fourth generation segmented routing structure
- Predictable, fast routing delay, independent of
fanout
• SelectIO™-Ultra Technology
- Up to 824 user I/Os
- 19 single-ended and six differential standards
- Programmable sink current (2 mA to 24 mA) per
I/O
- Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
- Differential Signaling
· 622 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
· Bus LVDS I/O
· Lightning Data Transport (LDT) I/O with current
driver buffers
· Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
· Built-in DDR input and output registers
- Proprietary high-performance SelectLink
Technology
· High-bandwidth data path
· Double Data Rate (DDR) link
· Web-based HDL generation methodology
• Supported by Xilinx Foundation Series™ and Alliance
Series™ Development Systems
- Integrated VHDL and Verilog design flows
- Compilation of 10M system gates designs
- Internet Team Design (ITD) tool
• SRAM-Based In-System Configuration
- Fast SelectMAP configuration
- IEEE 1532 support
- Partial reconfiguration
- Unlimited reprogrammability
- Readback capability
• 0.15 µm 8-Layer Metal Process with 0.12 µm
High-Speed Transistors
• 1.5V (VCCINT) Core Power Supply, Dedicated 3.3V
VCCAUX Auxiliary and VCCO I/O Power Supplies
• IEEE 1149.1 Compatible Boundary-Scan Logic Support
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS124 (v1.1) January 8, 2004
Product Specification
www.xilinx.com
1-800-255-7778
1
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Xilinx

XQR2V1000 Datasheet Preview

XQR2V1000 Datasheet

QPro Virtex-II 1.5V Radiation Hardened QML Platform FPGAs

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QPro Virtex-II 1.5V Radiation Hardened QML Platform FPGAs
R
Table 1: Virtex-II Field-Programmable Gate Array Family Members
CLB
(1 CLB = 4 slices = Max 128 bits)
Device
Syste
m Array
Gates Row x Col.
Slices
Maximum
Distributed
RAM Kbits
Multiplier
Blocks
XQR2V1000 1M
40 x 32 5,120
160
40
XQR2V3000 3M
64 x 56 14,336
448
96
XQR2V6000 6M
96 x 88 33,792
1,056
144
Notes:
1. See details in Table 2, "Maximum Number of User I/O Pads".
SelectRAM Blocks
18 Kbit
Blocks
40
96
144
Max RAM
(Kbits)
720
1,728
2,592
DCMs
8
12
12
Max I/O
Pads(1)
432
720
1,104
General Description
The QPro Virtex-II radiation hardened family includes plat-
form FPGAs developed for high performance, high-density,
aerospace designs that are based on IP cores and custom-
ized modules. The family delivers complete solutions for
telecommunication, networking, video, and DSP applica-
tions, including PCI, LVDS, and DDR interfaces.
The leading-edge 0.15 µm/0.12 µm CMOS 8-layer metal
process and the Virtex-II architecture are optimized for high
speed with low power consumption. Combining a wide vari-
ety of flexible features and a large range of densities up to
6 million system gates, the Virtex-II family enhances pro-
grammable logic design capabilities and is a powerful alter-
native to mask-programmed gates arrays and other
one-time-programmable devices. As shown in Table 1, the
QPro Virtex-II radiation hardened family comprises three
members, ranging from 1M to 6M system gates.
Packaging
Offerings include ball grid array (BGA) packages with
1.00 mm and 1.27 mm pitches. In addition to traditional
wire-bond interconnects, flip-chip interconnect is used in
some of the CGA offerings. The use of flip-chip interconnect
offers more I/Os than is possible in wire-bond versions of
the similar packages. Flip-chip construction offers the com-
bination of high pin count with high thermal capacity.
Table 2 shows the maximum number of user I/Os available.
The Virtex-II device/package combination table (Table 6 on
page 5) details the maximum number of I/Os for each
device and package using wire-bond or flip-chip technology.
Table 2: Maximum Number of User I/O Pads
Device
Wire-Bond
Flip-Chip
XQR2V1000
328
-
XQR2V3000
516
-
XQR2V6000 - 824
Radiation Assurance
The Virtex-II Radiation Hardened Platform FPGAs are
guaranteed for Total Ionizing Dose (TID) life and Single
Event Latch-Up immunity (SEL).
Total Ionizing Dose
Each Wafer Lot is sampled and tested per Method 1019.5 to
assure that device performance meets or exceeds the guar-
anteed DC electrical specification requirements, as well as
AC and Timing parameters at maximum guaranteed total
dose levels.
Single Event Latch-Up
The Radiation hardened Virtex-II technology incorporates a
thin epitaxial layer in the wafer manufacturing process for
latch-up immunity assurance. The qualified mask set is ver-
ified in a heavy ion environment under vacuum, and tested
with an LET that exceeds Space environment phenomenon,
to a fluence that exceeds 1E7 particles/cm2.
Single Event Upset
Additional experiments are conducted in heavy ion, proton,
and neutron environments in order to measure and docu-
ment the susceptibility and consequence of SEU(s). An
industry consortium oversees and validates the test meth-
ods, empirical data collected, and resulting analysis. Con-
clusions are published on the website as well as
International Conferences. The Single Event Effects Con-
sortium Reports can be found at http://www.xilinx.com/prod-
ucts/hirel_qml.htm
2
www.xilinx.com
DS124 (v1.1) January 8, 2004
1-800-255-7778
Product Specification
Datasheet pdf - http://www.DataSheet4U.net/


Part Number XQR2V1000
Description QPro Virtex-II 1.5V Radiation Hardened QML Platform FPGAs
Maker Xilinx
Total Page 30 Pages
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