74F109 Datasheet - Texas Instruments

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP

74F109 General Description

These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K input meeting the setup-time requirem.

74F109 Datasheet (586.73 KB)

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74F109

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Texas Instruments ↗

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586.73 KB

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Dual j-k positive-edge-triggered flip-flop.
SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A MARCH 1987 REVISED OCTOBER 1993

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74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP Texas Instruments

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74F109 General Description

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