| Part number | 74F109 |
|---|---|
| Download | 74F109 Datasheet (PDF) |
| File Size | 586.73 KB |
| Manufacturer | Texas Instruments |
| Description | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP |
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| Manufacturer | Part Number | Description |
|---|---|---|
National Semiconductor |
74F109 | Dual JK Positive Edge-Triggered Flip-Flop |
NXP Semiconductors |
74F109 | Positive J-K positive edge-triggered flip-flops |
Fairchild |
74F109 | Dual JK Positive Edge-Triggered Flip-Flop |
These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse.
