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74F109 Datasheet Dual Jk Positive Edge-triggered Flip-flop

Manufacturer: National Semiconductor (now Texas Instruments)

Overview: 54F/74F109 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop November 1994 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops.

The clocking operation is independent of rise and fall times of the clock waveform.

The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs.

Key Features

  • n Guaranteed 4000V minimum ESD protection. Ordering Code: See Section 0 Commercial Military 74F109PC 74F109SC (Note 1) 54F109DM (Note 2) 74F109SJ (Note 1) 54F109FM (Note 2) 54F109LM (Note 2) Package Number N16E J16A M16A M16D W16A E20A Package.

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