Part 74F109
Description Dual JK Positive Edge-Triggered Flip-Flop
Manufacturer National Semiconductor
Size 133.13 KB
National Semiconductor
74F109

Overview

The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.

  • Guaranteed 4000V minimum ESD protection. Ordering Code: See Section 0 Commercial Military