Datasheet4U Logo Datasheet4U.com

74F109 - Dual JK Positive Edge-Triggered Flip-Flop

Product Overview

📥 Download Datasheet

Datasheet preview – 74F109

Datasheet Details

Part number 74F109
Manufacturer Fairchild Semiconductor
File Size 79.72 KB
Description Dual JK Positive Edge-Triggered Flip-Flop
Datasheet download datasheet 74F109 Datasheet
Additional preview pages of the 74F109 datasheet.

Product details

Description

The F109 consists of two high-speed, completely independent transition clocked JK flip-flops.

The clocking operation is independent of rise and fall times of the clock waveform.

The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs.

📁 Similar Datasheet
  • 74F109 - Dual JK Positive Edge-Triggered Flip-Flop (National Semiconductor)
  • 74F109 - Positive J-K positive edge-triggered flip-flops (NXP)
  • 74F109 - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP (Texas Instruments)
  • 74F10 - Triple 3-input NAND gate (NXP)
  • 74F10 - Triple 3-Input NAND Gate (National Semiconductor)
  • 74F10 - TRIPLE 3-INPUT POSITIVE-NAND GATE (Texas Instruments)
  • 74F11 - Triple 3-Input AND Gate (National Semiconductor)
  • 74F11 - Triple 3-input NAND gate (NXP)
Other Datasheets by Fairchild Semiconductor
  • 74F10 - Triple 3-Input NAND Gate
  • 74F1056 - 8-Bit Schottky Barrier Diode Array
  • 74F1071 - 18-Bit Undershoot/Overshoot Clamp
  • 74F11 - Triple 3-Input AND Gate
  • 74F112 - Dual JK Negative Edge-Triggered Flip-Flop
  • 74F113 - Dual JK Negative Edge-Triggered Flip-Flop
Published: |