74F109
Overview
These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs.
| Part | 74F109 |
|---|---|
| Description | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP |
| Manufacturer | Texas Instruments |
| Size | 586.73 KB |
Related Datasheets
| Part Number | Manufacturer | Description |
|---|---|---|
| 74F109 | National Semiconductor | Dual JK Positive Edge-Triggered Flip-Flop |
| 74F109 | NXP Semiconductors | Positive J-K positive edge-triggered flip-flops |
| 74F109 | Fairchild Semiconductor | Dual JK Positive Edge-Triggered Flip-Flop |
| 74F10 | National Semiconductor | Triple 3-Input NAND Gate |
| 74F10 | Fairchild Semiconductor | Triple 3-Input NAND Gate |