74F109 Datasheet

The 74F109 is a Dual JK Positive Edge-Triggered Flip-Flop.

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Part Number74F109
ManufacturerNational Semiconductor
Overview The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows . n Guaranteed 4000V minimum ESD protection. Ordering Code: See Section 0 Commercial Military 74F109PC 74F109SC (Note 1) 54F109DM (Note 2) 74F109SJ (Note 1) 54F109FM (Note 2) 54F109LM (Note 2) Package Number N16E J16A M16A M16D W16A E20A Package Description 16-Lead (0.300" Wide) Molded Dual-i.
Part Number74F109
DescriptionDUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP
ManufacturerTexas Instruments
Overview These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inp. D-type flip-flops if J and K are tied together. The SN54F109 is characterized for operation over the full military temperature range of
* 55°C to 125°C. The SN74F109 is characterized for operation from 0°C to 70°C. SN54F109 . . . J PACKAGE SN74F109 . . . D OR N PACKAGE (TOP VIEW) 1CLR 1 1J 2 1K 3.
Part Number74F109
DescriptionPositive J-K positive edge-triggered flip-flops
ManufacturerNXP Semiconductors
Overview The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous ac.
* Industrial temperature range available (
*40°C to +85°C) DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate i.
Part Number74F109
DescriptionDual JK Positive Edge-Triggered Flip-Flop
ManufacturerFairchild Semiconductor
Overview The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows o. y by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009471 www.fairchildsemi.com 74F109 Truth Table Inputs SD L H L H H H H H CD H L L H H H H H CP X X J X X X I h I h X K X X X I I h h X Q H Q Q H L H .