ADS62P19 Datasheet | Texas Instruments

FEATURES - 2 Maximum Sample Rate: 250 MSPS - 11-Bit Resolution - Total Power: 1.25 W at 250 MSPS - Output Options: - DDR LVDS and Parallel CMOS - Programmable Gain: - Up to 6 d B for SNR and SFDR Trade-Off - DC Offset Correction - Crosstalk: 90 d B - Supports Input Clock Amplitude Down to 400 m VPP, Differential - Internal and External Reference Support - Package: 9-mm × 9-mm QFN-64 DESCRIPTION The ADS62P19 is part of a family of dual-channel, 11-bit, analog-to-digital converters (ADCs) with sampling rates up to 250 MSPS. The device bines high dynamic performance and low power consumption in a pact QFN-64 package. This functionality makes the device well-suited for multicarrier, wide-bandwidth munication applications. The ADS62P19 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. The device includes a dc offset correction loop that can be used to cancel ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel plementary metal oxide semiconductor (CMOS) digital output interfaces are available. Although the device includes internal references, the traditional reference pins and associated decoupling capacitors are eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (- 40°C to +85°C). ADS62Pxx High-Speed Family RESOLUTION 200 MSPS 210 MSPS 250 MSPS 11-bit ADS62C17 - ADS62P19 12-bit - ADS62P28 ADS62P29 14-bit - ADS62P48 ADS62P49 AT 170-MHz INPUT SFDR, d Bc SINAD, d BFS Analog power, W GAIN (d B) 0 6 0 6 - Table 1. Performance Summary ADS62P19 75 82 65.3 64 1 ADS62P28 78 84 68.7 65.8 0.92 ADS62P29 75 82 68.3 65.8 1 ADS62P48 78 84 70.1 66.3 0.92 ADS62P49 75 82 69.8 66.5...