ADS6425 Datasheet | Texas Instruments

.ti. ......................................................................................................................................................... SLWS197B - MARCH 2007 - REVISED JUNE 2009 QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE Features - Maximum Sample Rate: 125 MSPS - 12-Bit Resolution with No Missing Codes - 1.65-W Total Power - Simultaneous Sample and Hold - 70.3 d BFS SNR at Fin = 50 MHz - 83 d Bc SFDR at Fin = 50 MHz, 0 d B Gain - 79 d Bc SFDR at Fin = 170 MHz, 3.5 d B Gain - 3.5 d B Coarse Gain and up to 6 d B Programmable Fine Gain for SFDR/SNR Trade-Off - Serialized LVDS Outputs with Programmable Internal Termination Option - Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 m Vpp Differential - Internal Reference with External Reference Support - No External Decoupling Required for References - 3.3-V Analog and Digital Supply - 64 QFN Package (9 mm × 9 mm) - Pin patible 14-Bit Family (ADS644X - SLAS532) APPLICATIONS - Base-Station IF Receivers - Diversity Receivers - Medical Imaging - Test Equipment DESCRIPTION The ADS6425 is a high performance 12-bit, 125-MSPS quad channel ADC. Serial LVDS data outputs reduce the number of interface lines, resulting in a pact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes a 3.5 d B coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1d B steps up to 6d B. The output interface is 2-wire, where each ADC's data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (pared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS6425 also includes the traditional 1-wire interface that can be used at lower sampling...