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ADS6444 - Analog-to-Digital Converters

Download the ADS6444 datasheet PDF. This datasheet also covers the ADS6442 variant, as both devices belong to the same analog-to-digital converters family and are provided as variant models within a single manufacturer datasheet.

Description

The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65 MSPS quad channel A-D converters.

Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density.

Features

  • 1.
  • Maximum Sample Rate: 125 MSPS.
  • 14-Bit Resolution with No Missing Codes.
  • Simultaneous Sample and Hold.
  • 3.5dB Coarse Gain and up to 6dB Programmable Fine Gain for SFDR/SNR Trade-Off.
  • Serialized LVDS Outputs with Programmable Internal Termination Option.
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude down to 400 mVPP.
  • Internal Reference with External Reference Support.
  • No External Decoupling Required for Refe.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ADS6442-etcTI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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ADS60C160L 3 Quadrants Triacs ADV

Other Datasheets by Texas Instruments

Part Number Description
ADS6444-EP Analog-to-Digital Converters
ADS6442 Analog-to-Digital Converters
ADS6443 Analog-to-Digital Converters
ADS6445 Analog-to-Digital Converters
ADS6445-EP Analog-to-Digital Converters

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS Check for Samples: ADS6445, ADS6444, ADS6443, ADS6442 FEATURES 1 • Maximum Sample Rate: 125 MSPS • 14-Bit Resolution with No Missing Codes • Simultaneous Sample and Hold • 3.5dB Coarse Gain and up to 6dB Programmable Fine Gain for SFDR/SNR Trade-Off • Serialized LVDS Outputs with Programmable Internal Termination Option • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude down to 400 mVPP • Internal Reference with External Reference Support • No External Decoupling Required for References • 3.
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