Datasheet Summary
CDC341 1-LINE TO 8-LINE CLOCK DRIVER
D Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
D TTL-patible Inputs and Outputs D Distributes One Clock Input to Eight
Outputs
D Distributed VCC and Ground Pins Reduce
Switching Noise
D High-Drive Outputs (- 48-mA IOH,
48-mA IOL)
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D Packaging Options Include Plastic
Small-Outline (DW) Packages
SCAS333D
- DECEMBER 1992
- REVISED OCTOBER 1998
DW PACKAGE (TOP VIEW)
VCC 1 1G 2 2G 3 A4 P0 5 P1 6
VCC 7 2Y4 8 2Y3 9 GND 10
20 VCC 19 1Y1 18 1Y2 17 GND 16 1Y3 15 1Y4 14 GND 13 2Y1 12 2Y2 11 GND description
The CDC341 is a...