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CDC318A - 1-Line To 18-Line Clock Driver

General Description

The CDC318A is a high-performance clock buffer designed to distribute high-speed clocks in PC applications.

This device distributes one input (A) to 18 outputs (Y) with minimum skew for clock distribution.

The CDC318A operates from a 3.3-V power supply.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications D Output Skew, tsk(o), Less Than 250 ps D Pulse Skew, tsk(p), Less Than 500 ps D Supports up to Four Unbuffered SDRAM Dual Inline Memory Modules (DIMMs) D I2C Serial Interface Provides Individual Enable Control for Each Output D Operates at 3.3 V D Distributed VCC and Ground Pins Reduce Switching Noise D 100-MHz Operation D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015 D Packaged in 48-Pin Shrink Small Outline (DL) Package description The CDC318A is a high-performance clock buffer designed to distribute high-speed clocks in PC applications.